HFT CORE SYSTEMS

DRAM and memory bandwidth under contention

Lesson 19 of 96Phase 02: CPU and memory systems
Video lesson coming soon

The written objectives and hands-on lab are available now.

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Learning objectives

What you should understand

  1. Separate memory latency from sustainable bandwidth
  2. Recognize channel and controller contention
  3. Measure noisy-neighbor impact on tail latency

Lab

Hands-on exercise

Run a latency-sensitive reader beside adjustable bandwidth pressure.

Deliverable

Evidence of completion

A contention curve showing bandwidth, percentiles and saturation point.

Prerequisite
EP 18

Phase 02

CPU and memory systems

Full curriculum