cppvalleyC++ · Systems · Low Latency · HFT
HFT Core Systems

HFT CORE SYSTEMS

NUMA placement and ownership

Lesson 17 of 96Phase 02: CPU and memory systems
Video lesson coming soon

The written objectives and hands-on lab are available now.

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Learning objectives

What you should understand

  1. Map CPU and memory locality across NUMA nodes
  2. Control first-touch placement and thread affinity
  3. Detect remote-memory penalties and ownership drift

Lab

Hands-on exercise

Measure local and remote memory access with explicit placement.

Deliverable

Evidence of completion

A topology map and NUMA latency/bandwidth comparison.

Prerequisite
EP 16

Phase 02

CPU and memory systems

Full curriculum
09Cache geometry and address decomposition10Cache coherence: MESI/MOESI without the bus-lock myth11False sharing and constructive sharing12Out-of-order execution and the dependency graph13Branch prediction and data-dependent control flow14SIMD with feature dispatch15TLBs and page walks16Huge pages: explicit HugeTLB vs. THP17NUMA placement and ownership18Prefetching: hardware, software, and pointer chasing19DRAM and memory bandwidth under contention20Phase gate: data-oriented redesign