HFT CORE SYSTEMS

Out-of-order execution and the dependency graph

Lesson 12 of 96Phase 02: CPU and memory systems
Video lesson coming soon

The written objectives and hands-on lab are available now.

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Learning objectives

What you should understand

  1. Reason about dependencies rather than source order
  2. Identify instruction-level parallelism limits
  3. Separate latency-bound from throughput-bound code

Lab

Hands-on exercise

Benchmark dependent and independent arithmetic chains with matching work.

Deliverable

Evidence of completion

An instruction-dependency graph backed by cycle measurements.

Prerequisite
EP 11

Phase 02

CPU and memory systems

Full curriculum